Referring to FIG. 1, a cross sectional view of a conventional Gallium Arsenide (GaAs) pHEMT epitaxial structure 10 is shown during fabrication. Common GaAs pHEMT transistors used in switching applications have been available for over a decade. The transistors are produced by growing epitaxial layers 12 on a semi-insulating GaAs substrate 14 utilizing either Molecular Beam Epitaxy (MBE) or Metal-Organic Chemical Vapor Deposition Epitaxy (MOCVD) techniques. An optional updoped layer 16 is sometimes included. The layer 16 serves as an etch stop for etching an upper doped GaAs layer 18 during subsequent device fabrication. However, similar performances have been achieved without the etch stop layer 16 present.
Referring to FIG. 2, a simplified cross-sectional view of a conventional pHEMT 20 is shown. A source and a drain of the pHEMT 20 are formed by the deposition and sintering of an ohmic metallization. A gate/channel region is formed by performing a channel recess etch prior to a deposition of a Schottky gate metallization. A single recess etch structure is shown in FIG. 2, but multiple recesses are common to optimize device characteristics. Multiple gate structures are also fabricated for increased breakdown voltage and electrical isolation. A device-to-device isolation implant is formed by an ion implantation and by not removing the implant damage by subsequent anneals. The top surface of the transistor is passivated by the deposition of a dielectric using Plasma Enhanced Chemical Vapor Deposition (PECVD) techniques. Silicon nitride is commonly used as the dielectric. The device formed by the conventional technique has characteristics of high isolation, moderate radio-frequency (RF) power handling, frequency responses up through 40 gigahertz (GHz), very low current draw that is essentially zero except when switching states, and rise times (i.e., 10% to 90% of an RF envelope) and fall times (i.e., 90% to 10% of the RF envelope) of 50 to 100 nanoseconds.
While the rise times and the fall times are more than adequate, a difficulty with switching applications using the conventional pHEMT structures lies in a device gate lag time, or settling time, (i.e., the time for the RF envelope to increase from 90% to 98% or decrease from 10% to 2%). The best gate lag times reported for conventional pHEMTs are in the range of several hundred microseconds, which increases the total switching time of the pHEMT 20 by a factor of several thousand over the rise/fall times.
Referring to FIG. 3, a partial cross-sectional view of the conventional pHEMT 20 is shown. As illustrated, the gate of the transistor and a depletion region in the n-type AlGaAs layer form a resistor-capacitor (RC) charging and discharging network. The RC charging and discharging network limits a rate at which channel charge and any trapped charged surface states can be injected and removed from the device.